Successful candidates will be working on the following:
- Block level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level. The skills required are SV/UVM/UVM_REG/Randomization/Coverage/SVA.
Must have between 8-12 years of combined experience with the below:
- 5 years minimum ASIC DV experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.
- Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking.
- Experience in debugging RTL & Gate level simulations
- Part of multiple tapeouts with high quality verification.
Required: Bachelor's, Computer Engineering and/or Electrical Engineering
Preferred: Master's, Computer Engineering and/or Electrical Engineering
Reporting, Debugging, ASIC, Engineering, Presentation Other