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Senior Design Verification Engineer
3 weeks ago
San Diego, California, US

Job Description

Successful candidates will be working on the following:

  • Block level digital IP verification using constraint-random coverage methodologies at both RTL and Gate Level. The skills required are SV/UVM/UVM_REG/Randomization/Coverage/SVA.


Minimum Qualifications

Must have between 8-12 years of combined experience with the below:

  • SV/UVM/UVM_REG/Randomization/Coverage/SVA.
  • 5 years minimum ASIC DV experience and working knowledge of Object-Oriented SystemVerilog principles using UVM/OVM/VMM methodologies.


Preferred Qualifications

  • Extensive hand on experience in verifying digital blocks, building UVM based TB, writing UVM sequences, constraint-random testcases, using regModel (UVM_REG) API, drivers, monitors, scoreboard, functional coverage (covergroups), assertions (SVA), simulations, regression, debug, bug reporting/tracking.
  • Experience in debugging RTL & Gate level simulations
  • Part of multiple tapeouts with high quality verification.


Educational Requirements

Required: Bachelor's, Computer Engineering and/or Electrical Engineering

Preferred: Master's, Computer Engineering and/or Electrical Engineering



Job Requirements

Reporting, Debugging, ASIC, Engineering, Presentation Other


Job Code: 50141092

Reach Out to a Recruiter

Recruiter Naveen
Phone +8586050549