• SI/PI Simulation: Run pre- and post-layout 2D/3D simulations (Cadence PowerSI, ADS, HSPICE) to optimize high-speed channels and power distribution networks.
• Manufacturing Troubleshooting: Provide engineering support for operations and production, root-causing high-speed signal failures and yield issues from the factory floor.
• Lab Validation: Use lab equipment (VNA, TDR, high-bandwidth oscilloscopes) to measure S-parameters, impedance, and eye diagrams, correlating physical data with simulations.
• Interface Optimization: Work with high-speed links and interfaces (SerDes, PAM4, NRZ, DDR) to ensure signal compliance and jitter reduction.
• Cross-Functional Collaboration: Partner with hardware design, test engineering, and manufacturing teams to review layouts, resolve DFM challenges, and validate ECOs.

• Bachelor’s or Master’s degree in Electrical Engineering or a related field.
• 3–5 years of relevant experience in signal integrity or hardware design.
• Knowledge of transmission line theory and high-speed circuit fundamentals, with experience using signal-integrity simulation and 2D/3D field-solver tools.

• Experience with laboratory equipment such as oscilloscopes, TDR, or VNA.
• Experience with IBIS, HSPICE, ADS, MATLAB, Cadence PowerSI AC/DC, or Allegro.
• Exposure to high-speed interfaces and links such as SerDes, LVDS, CML, DDR, NRZ, or PAM4, including high-speed PCB/package development or PI analysis.

• Engineering support for operations and manufacturing production.
• 3 years of experience are required.

The Company offers the following benefits for this position, subject to applicable eligibility requirements: medical insurance, dental insurance, vision insurance, 401(k) retirement plan, life insurance, long-term disability insurance, short-term disability insurance, paid parking/public transportation, paid time off, paid sick and safe time, hours of paid vacation time, weeks of paid parental leave, and paid holidays annually – as applicable.